This invention relates to a cell library database used in computer-aided design (CAD) of logical devices such as semiconductor integrated circuits and a design aiding system using the cell library database. Particularly, the invention relates to a cell library database and a design aiding system appropriate for logical simulation used for design verification of logic, delay, or the like, of logical devices ,failure analysis, software development tools, or the like.
Hitherto, in computer-aided design (CAD) of logical devices such as semiconductor integrated circuits, power consumption has been reduced based on various techniques and concepts with an increase in the importance of low power consumption in chips, systems, apparatus, etc., of LSI, etc.
One of the techniques of reducing power consumption is a design technique of changing a conventional single power supply to multiple power supplies. According to the design technique, in LSI, for example, conventional power supply voltage is used for an interface circuit with the outside and the power supply voltage is decreased for internal circuitry, thereby reducing power consumption. Based on a similar concept, conventional power supply voltage is given to blocks in LSI requiring high-speed performance and lower power supply voltage is given to blocks not requiring high speed, whereby it is also made possible to reduce power consumption of the LSI.
To conduct circuit design of LSI as exemplified above, there is a possibility that the same standard cell may be used under different power supply voltages. Thus, in logical simulation, it is necessary to provide cell library databases corresponding to the power supply voltages even for the cells having the same logic and use the provided cell library databases to verify the design. JP-A-6-260557 discloses a semiconductor design aiding system for verifying design of LSI with multiple power supplies mixed. The contents of the semiconductor design aiding system will be discussed briefly.
The semiconductor design aiding system in the related art is as follows: When a circuit diagram is drawn, the cells having the same logical function are represented by the same symbol mark. Which power supply voltage each cell operates on is indicated in the circuit diagram, whereby when the circuit diagram is expanded to a net list, the cell is converted into a predetermined cell name based on the combination of the corresponding function and operation power supply voltage, whereby the logical information and electrical characteristics of the corresponding logical cell in the cell library database are used to execute logical simulation.
FIG. 8 illustrates the contents of the cell library database used in the related art example. Cell library registration information contains information of a symbol mark 501 of a cell (NAND gate 510), a logical relation table 502 of input signals A and B and an output signal Y, and a delay time table 503 listing the propagation delay times until the output signal C is output after the input signals A and B change.
Another technique aside from the above-described technologies of reducing power consumption is as follows: A control function is provided wherein when the circuit operation is not required, power supply to the corresponding logical block is stopped and when the circuit operation is required, power is supplied to the logical block, whereby fruitless circuit operation is reduced for decreasing the power consumption of the whole circuitry.
With the design aiding system in the related art described above, logical simulation of a semiconductor integrated circuit with multiple power supplies mixed can be executed; however, the logical information and the delay time information are described as registration information in the cell library database based on the premise that power is always supplied, thus if logical simulation is executed for a circuit having a control function of supplying power to logical blocks and stopping power supply to logical blocks as in the third technique of reducing power consumption as described above, all logical blocks always operate. Thus, if the whole circuitry is logically simulated at a time, it is impossible to verify design of the circuit specifications as essentially assumed and the circuit for controlling power supply and power supply stop and the logical blocks must be logically simulated and checked separately. Since logical simulation of the whole circuitry cannot be accomplished in batch, the connection relationship between the logical blocks, etc., is verified by another worker or function simulation or the like; the design verification job becomes intricate.
It is therefore an object of the invention to provide a cell library database and a design aiding system for making it possible to logically simulate the whole of even a logical device comprising a control function of power supply and power supply stop in batch and consequently execute logical simulation accurately and easily.
To the end, according to first aspect of the invention, there is provided a cell library database having function information of standard cells which are basic circuit forming a logical device, each of the standard cell having at least one of power supply terminal as logical terminal, the function information of the standard cell containing logical information of the power supply terminal relative to an output terminal.
According to second aspect of the invention, there is provided a cell library database having function information of standard cells which are basic circuit forming a logical device, each of the standard cell having at least one of power supply terminal as logical terminal, the function information of the standard cell contains delay information of the power supply terminals relative to an output terminal.
According to third aspect of the invention, there is provided a cell library database having function information of macro cells which are functional circuits forming a logical device, each of the macro cell having at least one of power supply terminal as logical terminals, and the function information of the macro cell containing logical information of the power supply terminal relative to an output terminal.
According to fourth aspect of the invention, there is provided a cell library database having function information of macro cells which are functional circuits forming a logical device, each of the macro cell having at least one of power supply terminal as logical terminals and the function information of the macro cell containing delay information of the power supply terminals relative to an output terminal.
According to fifth aspect of the invention, there is provided a design aiding system using a cell library database as described above for aiding design of logical devices.
In the cell library database, the standard cell comprises one or more power supply terminals as logical terminals and the function information of the standard cell for each type in the cell library database contains the logical information or the delay information of the one or more power supply terminals relative to the output terminal. The design aiding system uses the cell library database to execute logical simulation, or the like.
The standard cell is a basic circuit forming a logical device; for example, it corresponds to a gate element such as a NAND gate or a NOR gate, a flip-flop (latch), or the like. Power supply potential Vcc, ground potential GND, etc., is supplied to the power supply terminal, and different potentials of 5 [V], 3.3 [V], 2.5 [V], 1.8 [V], or the like, are used as the power supply potential Vcc. The logical information of the standard cell corresponds to a logic relation table of the input and power supply terminals to the output terminal, etc., for example. As the handled signal values, the logical values xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9cHxe2x80x9d, xe2x80x9cLxe2x80x9d, xe2x80x9cXxe2x80x9d corresponding to xe2x80x9cundefinedxe2x80x9dare used and in addition, xe2x80x9c↑xe2x80x9d and xe2x80x9c↓xe2x80x9d are used as transition state signal values if the rising state and the falling state of a signal are significant; xe2x80x9cZxe2x80x9d representing a high impedance state in a tristate element also becomes a real signal value. The delay information of the standard cell corresponds to a propagation delay occurring when a signal propagates in the element, an inertia delay determined in association with energy for driving the element, and the like. Further, the logical simulation mentioned here has a wide range of applications of not only design verification of logic, delay, etc., of a logical device, but also failure analysis and software development tools.
Since the standard cell comprises one or more power supply terminals as logical terminals and the function information of the standard cell for each type in the cell library database has the logical information of the one or more power supply terminals relative to the output terminal, the circuit operation difference caused by power supply or power supply stop can be simulated even for a logical device containing a logical block with power supply undergoing switching control. Thus, it is made possible to verify logic design of the whole logical device in batch. Since the function information has the delay information of the one or more power supply terminals relative to the output terminal, it is made possible to execute design verification of delay considering the power supply timing. To sum up, logical simulation of a logical device with multiple power supplies mixed can be executed and in addition, the whole of even a logical device comprising a control function of power supply and power supply stop for reducing power consumption can also be executed in batch; consequently, it is made possible to conduct logical simulation and design aiding accurately and easily.
In the cell library database, the macro cell comprises one or more power supply terminals as logical terminals and the function information of the macro cell for each type in the cell library database contains the logical information or the delay information of the one or more power supply terminals relative to the output terminal. The design aiding system uses the cell library database to execute logical simulation, or the like.
The macro cell is a circuit forming a logical device and having a functional unit; for example, it corresponds to a register, a data selector, a level shifter, an adder, memory, or the like. Power supply potential Vcc, ground potential GND, etc., is supplied to the power supply terminal, and different potentials of 5 [V], 3.3 [V], 2.5 [V], 1.8 [V], etc., are used as the power supply potential Vcc. The logical information of the macro cell corresponds to a logic relation table of the input and power supply terminals to the output terminal, etc., for example. As the handled signal values, the logical values xe2x80x9c1,xe2x80x9d xe2x80x9c0,xe2x80x9d xe2x80x9cL,xe2x80x9d xe2x80x9cX,xe2x80x9d corresponding to xe2x80x9cundefinedxe2x80x9d are used and in addition, xe2x80x9c↑xe2x80x9d and. xe2x80x9c↓xe2x80x9d are used as transition state signal values if the rising state and the falling state of a signal are significant; xe2x80x9cZxe2x80x9d representing a high impedance state in a tristate element also becomes a real signal value. The delay information of the macro cell corresponds to a propagation delay occurring when a signal propagates in the macro cell, an inertia delay determined in association with drive energy, and the like. Further, the logical simulation mentioned here has a wide range of applications of not only design verification of logic, delay, etc., of a logical device, but also failure analysis and software development tools.
Since the macro cell comprises one or more power supply terminals as logical terminals and the function information of the macro cell for each type in the cell library database has the logical information of the one or more power supply terminals relative to the output terminal, the circuit operation difference caused by power supply or power supply stop can be simulated even for a logical device containing a logical block with power supply undergoing switching control. Thus, it is made possible to verify logic design of the whole logical device in batch. Since the function information has the delay information of the one or more power supply terminals relative to the output terminal, it is made possible to execute design verification of delay considering the power supply timing. To sum up, logical simulation of a logical device with multiple power supplies mixed can be executed and in addition, the whole of even a logical device comprising a control function of power supply and power supply stop for reducing power consumption can also b e executed in batch; consequently, it is made possible to conduct logical simulation and design aiding accurately and easily.
The cell library databases of the first or second aspect of the invention can be used to execute simulation at a gate level, the cell library databases of the third or fourth aspect of the invention can be used to execute simulation at a function level. And the cell library databases of the invention can be used in combination to execute simulation at a gate and function mix level. Further, if the cell library databases of the third or fourth of the invention are applied to high-order modules in a design hierarchy, simulation at a module level can be executed.
The logical devices to which the cell library database and the design aiding system of the invention are applied include not only the semiconductor integrated circuits of IC, LSI, VLSI, ULSI, etc., but also a logical device comprising discrete parts mounted on a board.